Light modulating mirror devices have been developed in which a mirror or reflector is can be positioned at various locations to either direct the impinging light to one location or to direct the impinging light to another location.
When a voltage is applied to one region housing the mirror, the mirror is moved so that the impinging light is directed to a first location. When the voltage is removed or applied to another region housing the mirror, the mirror is moved so that the impinging light is directed to a second location.
Such a device can be implemented in a variety of optical applications. For example, U.S. Pat. No. 5,061,049, issued on Oct. 29, 1991, entitled “Spatial Light Modulator and Method,” describes a spatial light modulator with a movable mirror.
Spatial light modulators are transducers that modulate incident light in a spatial pattern corresponding to an electrical or optical input. The incident light may be modulated in its phase, intensity, polarization, or direction, and the light modulation may achieved by a variety of materials exhibiting various electrooptic or magnetoopotic effects and by materials that modulate light by surface deformation.
An example of a prior art single pixel electrostatic (rigid) movable mirror device is illustrated by FIG. 1. The pixel, generally denoted 20, is basically a plate (flap) covering a shallow well and includes silicon substrate 22, insulating spacer 24, metal hinge layer 26, metal plate layer 28, plate 30 formed in layers 26-28, and plasma etch access holes 32 in plate 30. The portions 34 & 36 of hinge layer 26 that are not covered by plate layer 28 form torsion hinges (torsion rods) attaching beam 30 to the portion of layers 26-28 supported by spacer 24. Electrodes 40, 42, 46, and 41 run between spacer 24 and substrate 22 and are isolated from substrate 22 by silicon dioxide layer 44.
The design of FIG. 1 allows that the plate metal be as thick as desired and the hinge metal be as thin as desired without the problems of step coverage of the hinge metal over the plate metal and that the spacer surface under the beam metal is not exposed to processing side effects which would arise if the hinge were formed as a rectangular piece on the spacer prior to deposition of the plate metal.
Pixel 20 is operated by applying a voltage between metal layers 26-28 and electrodes 42 or 46 on substrate 22: beam 30 and the electrodes form the two plates of an air gap capacitor and the opposite charges induced on the two plates by the applied voltage exert electrostatic force attracting beam 30 to substrate 22, whereas electrodes 40 and 41 are held at the same voltage as beam 30. This attractive force causes beam 30 to twist at hinges 34 and 36 and be deflected towards substrate 22.
FIG. 1 also indicates the reflection of light from deflected beam 30 as may occur during operation of a deformable mirror device. The deflection of beam 30 can be a highly non-linear function of the applied voltage because the restoring force generated by the twisting of hinge 34 is approximately a linear function of the deflection but the electrostatic force of attraction increases as a function of the reciprocal of the distance between the closest corner of beam 30 and substrate 22.
Conventional optical switches provide single path switching for single lasers or single beam of light.
Therefore, it is desirable to provide an optical switching system that is capable of multiple sub-pathway switching without negatively impacting the switching speed. Furthermore, it is desirable to provide an optical switching system that is capable of handling multiple lasers or beams of light without negatively impacting the switching speed.
It is noted that higher integration of semiconductor devices is desired for superior performance and/or reducing the price of electronic devices.
Accordingly, three-dimensional semiconductor devices having a stacked structure have been fabricated, wherein the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. An example of such a structure is illustrated in FIG. 29.
In FIG. 29, a first layer 2110 is formed. Upon the first layer 2110, circuits 2205 and 2210 are formed. In this example, circuits 2205 and 2210 are formed on the same plane of layer 2110. Wiring or conductive traces 2310 are formed between circuits 2205 and 2210.
Upon first layer 2110, a second layer 2120 is formed. It is noted that an air gap may be formed between first layer 2110 and second layer 2120.
Upon the second layer 2120, circuits 2215 and 2220 are formed. In this example, circuits 2215 and 2220 are formed on the same plane of layer 2120. Wiring or conductive traces 2325 are formed between circuits 2215 and 2220.
Upon second layer 2120, a third layer 2130 is formed. It is noted that an air gap may be formed between second layer 2120 and third layer 2135.
Upon the third layer 2130, circuits 2225, 2230, and 2235 are formed. In this example, circuits 2225, 2230, and 2235 are formed on the same plane of layer 2130. Wiring or conductive traces 2340 and 2345 are formed between circuits 2225, 2230, and 2235.
Upon third layer 2130, a fourth layer 2140 is formed. It is noted that an air gap may be formed between third layer 2130 and fourth layer 2140.
Upon the fourth layer 2140, circuits 2240, 2245, and 2250 are formed. In this example, circuits 2240, 2245, and 2250 are formed on the same plane of layer 2140. Wiring or conductive traces 2360 and 2365 are formed between circuits 2240, 2245, and 2250.
To provide electrical connectivity between layers, wiring or conductive traces 2425 and 2475 are vertically formed between layers 2110, 2120, 2130, and 2140. Wiring or conductive traces 2305, 2315, 2320, 2330, 2335, 2350, 2355, and 2370 are formed to provide electrical connectivity between the various circuits and vertical conductive traces 2425 and 2475.
It is noted that wiring or conductive traces 2425 and 2475 may be integral with wiring or conductive traces 2305, 2315, 2320, 2330, 2335, 2350, 2355, and 2370.
Another example of a stacked structure is disclosed in Published US Patent Application Number 2012/0171861. The entire content of Published US Patent Application Number 2012/0171861 is hereby incorporated by reference.
In these conventional devices, the conductive traces that provide connectivity between levels or layers include 90 degree bends. These 90 degree bends can produce heat, consume power, and radiate noise.
Moreover, it is desirable to provide a three-dimensional circuit architecture that realizes less heat, less power consumption, optimally shorter paths, and higher connectivity options.
Furthermore, it is desirable to have a three dimensional circuit or device that is confined to a two dimensional substrate.